When operating in card-emulation mode, a near field communication (NFC) device that operates according to the ISO14443 standard may use passive load modulation to communicate to the card reader/writer device. When doing so, the NFC device varies the load on a loop antenna in a way that can be sensed by the card reader/writer and such that it can decode the communicated bits.
A clear trend in NFC devices (e.g. in smart phones) is a decrease in the physical size of the loop antenna. When operating in card-emulation mode, the decrease in antenna size results in decreased signal strength received by the card reader/writer, under some circumstances to below the level required by the ISO14443 standard. To overcome this problem, the standard was recently amended with a new communication mode, labelled “active PICC transmission” (where PICC stands for proximity integrated circuit card, which is emulated in card-emulation mode). In this active PICC transmission mode, rather than varying the passive load on its antenna, the NFC device actively transmits a signal to the card reader/writer. This active mode allows larger signal strengths to be generated from a small NFC antenna, to a level that is compliant with the standard.
When operating in active PICC transmission mode, there is a new specification that the NFC device has to obey: the signal that is transmitted to the card reader/writer has to be imposed on a carrier signal that is synchronous to the unmodulated carrier that is transmitted at the same time by the card reader/writer. One way of achieving this is disclosed in US2015/0063517. In that disclosure, a digital phase-locked loop (PLL) is used that locks to the incoming carrier (generated by the card reader/writer) before active transmission commences. Right before active transmission starts, the PLL settings are frozen such that the PLL continues to generate a signal that is synchronous to the card reader/writer carrier. This PLL output signal is then used as the carrier to which the active transmission symbols are imposed.
FIG. 1 shows a block diagram of a PLL 100 disclosed by US2015/0063517. The output clkFc is synchronized to an input signal Frx by modulating the post divider ratio /P in a fractional manner using a digital PLL.
The digital PLL comprises a digital phase detector 110, digital loop filter 115, and sigma delta modulator 120. The digital phase detector 110 receives the input signal Frx and a feedback signal, and outputs a phase error between these two signals. The digital loop filter 115 receives the phase error from the digital phase detector 110, performs a filtering operation on the phase error, and provides an input signal to the sigma-delta modulator 120. The sigma-delta modulator 120 provides a control signal Pctrl to post divider 130 of a further phase locked loop.
The further phase locked loop comprises a phase detector 135, loop filter 140, frequency controlled oscillator 145, feedback divider 125 and post divider 130. The phase detector 135 is configured to determine a phase difference between a reference signal Fref and a feedback signal output from the feedback divider 125. The loop filter 145 receives the output from the phase detector 135, performs a filtering operation, and provides the result as a control input to the frequency controlled oscillator 145. The output clkHF from the frequency controlled oscillator 145 is provided to the feedback divider 125, which divides the frequency of clkHF by a ratio /M, and provides the result as the feedback signal to the phase detector 135. The output clkHF from the frequency controlled oscillator 145 is also provided to the post-divider 135, which divides the frequency of clkHF by a ratio /P.
The output clkFc of the post-divider 130 is the output signal clkFc that is synchronized to the incoming carrier signal Frx by controlling the post-divider ratio /P in a fractional manner using the sigma-delta modulator 120. The instantaneous integer division ratio /P is varied over time, yielding a non-integer average division ratio. As such, the output signal clkFc of the post-divider 130, being equal in frequency to Frx, can be used directly as the carrier that is to be transmitted back to the card reader/writer.
A carrier signal that is oversampled is desirable in some circumstances. For instance, oversampling may spread a quantization error of the DAC over a large frequency range, or ensure that DAC spectral replicas appear at high enough frequencies to be filtered effectively.
An arrangement that allows a synchronized, oversampled carrier signal is therefore desired.